The present invention relates generally to the fabrication of planar lightwave circuits. More particularly, the present invention relates to a method and system for fabricating a top clad for a planar lightwave circuit.
Planar lightwave circuits (PLCs) comprise fundamental building blocks for the modern fiberoptic communications infrastructure. Planar lightwave circuits are generally devices configured to transmit light in a manner analogous to the transmission of electrical currents in printed circuit boards and integrated circuit devices. Examples include arrayed waveguide grating devices, integrated wavelength multiplexers/demultiplexers, optical switches, optical modulators, wavelength-independent optical couplers, and the like.
PLCs generally involve the provisioning of a series of embedded optical waveguides upon a semiconductor substrate, with the optical waveguides fabricated from a silica glass. PLCs are constructed using the advanced tools and technologies developed by the semiconductor industry. Modern semiconductor electronics fabrication technology can aggressively address the increasing need for integration is currently being used to make PLCs. By using manufacturing techniques closely related to those employed for silicon integrated circuits, a variety of optical elements can be placed and interconnected on the surface of a silicon wafer or similar substrate. This technology has only recently emerged and is advancing rapidly with leverage from the more mature tools of the semiconductor-processing industry.
PLCs are constructed with a number of waveguides precisely fabricated and laid out across a silicon wafer. A conventional optical waveguide comprises an un-doped silica bottom clad layer, with at least one waveguide core formed thereon, and a cladding layer covering the waveguide core, wherein a certain amount of at least one dopant is added to both the waveguide core and the cladding layer so that the refractive index of the waveguide core is higher than that of the cladding layer. Fabrication of conventional optical waveguides involves the formation of an un-doped silica layer as the bottom clad (BC), usually grown by thermal oxidation upon a silicon semiconductor wafer. The core layer is a doped silica layer, which is deposited by either plasma-enhanced chemical vapor deposition (PECVD) or flame hydrolysis deposition (FHD). An annealing procedure then is applied to this core layer (heated above 1000C) not only to expel the undesired chemical substance such as the radicals with bonded hydrogen but also to reduce the inhomogenities of refractive index within the core layer. The waveguide pattern is defined by photolithography on the core layer, and reactive ion etch (RIE) is used to remove the excess doped silica to form waveguide core. A SiO2 cladding layer is then formed through a subsequent deposition process. Finally, the wafer is cut into multiple PLC dies and packaged according to their particular applications.
Prior art FIG. 1 shows a cross-section view of a conventional planar optical waveguide. As depicted in FIG. 1, the planar optical waveguide includes three doped SiO2 glass cores 10a-10c formed over a SiO2 silica bottom clad 12. A BPSG top cladding layer 11 covers both the cores 10a-c and the bottom clad 12. As described above, the refractive index of the cores 10a-c is higher than that of the top cladding layer 11 and the bottom clad 12. Consequently, optical signals are confined axially within cores 10a-c and propagate lengthwise through cores 10a-c. The cores 10a-c are typically doped with Germanium to increase their index of refraction.
Prior art FIGS. 2A through 2C depict a top clad deposition process wherein three waveguide cores 21-23 are covered during a deposition process to form the top clad (e.g., top cladding layer 11). A well known problem with the fabrication of complex PLC devices is the gap fill of high aspect ratio areas between optical waveguide cores during top clad deposition. FIG. 2A shows three cores 21-23 out of the numerous waveguide cores comprising, for example, a 16 channel arrayed waveguide grating device. FIG. 2B shows three waveguides 21-23 at an intermediate step of the top clad deposition process. As shown in FIG. 2B, the gaps between cores 21-23 have been partially filled by the top clad layer 25. Subsequently, as shown in FIG. 2C, when the top clad deposition process is complete, the gaps between cores 21-23 are completely filled and the top clad layer 26 is completely flat and without voids.
Prior art FIG. 3 shows the problems which occur during a top clad deposition process of a highly integrated PLC device. FIG. 3 shows three cores 31-33 which are more closely spaced with respect to waveguides 21-23 of FIG. 2. As is well known, the closely spaced cores 33-31 present high aspect ratio gaps between them which must be filled during the top clad deposition and anneal process. The high aspect ratio of the gaps causes micro voids 41 and 42 to form as top clad layer 37 is deposited. The voids 41-42 are serious defects which significantly affect the performance of the waveguides comprising cores 31-33. In a case where the defects are not so significant as voids, there may be low density areas within the gaps instead of voids. Crystallization, which also adversely affects the performance of the waveguides, will develop in these low density areas.
One solution to this problem is to utilize a very gradual top clad xe2x80x9cbuildupxe2x80x9d process, wherein a number of deposition and anneal cycles are used to gradually buildup the thickness of the top clad layer. Successive thin top clad layers (e.g., typically 6 to 7 layers at minimum) are deposited and annealed in an attempt to avoid the formation of voids. While this solution is somewhat effective in filling high aspect ratio gaps, the large number of deposition and anneal cycles greatly decreases the throughput of the fabrication line.
Another solution to this problem is to use a high flow rate of a Boron dopant gas during the top clad buildup process, wherein the top clad is fabricated with a higher than normal weight percentage of Boron (e.g., greater than 6 wt %). The higher concentration of Boron dopant promotes better reflow characteristics of the top clad layer during the anneal process, thereby providing better gap filling capability. The better gap filling capability of a high Boron top clad process more effectively fills the gap between two closely spaced cores having a higher aspect ratio. The drawback to this solution however, is the fact that a high Boron top clad is much more susceptible to corrosion problems. High Boron concentrations within the silica matrix leads to a much higher corrosion susceptibility compare to the low Boron concentration silica glass. The corrosion can cause significant reliability problems for the PLC device, for example, insertion loss can become worse after prolonged exposure to high temperature and high humidity environment conditions.
Thus what is needed is a solution that can effectively fill high aspect ratio gaps between waveguide cores of an arrayed waveguide grating PLC device. What is needed is a solution that promotes better reflow characteristics during the anneal process and better gap filling capability while still maintaining good corrosion resistance. What is needed is a solution that can fill high aspect ratio gaps without adding an excessive amount of time to the overall device fabrication process. The present invention provides a novel solution to the above requirements.
The present invention is a method and system for a combination of high Boron and low Boron top clad fabrication process for a planer lightwave circuit. The present invention provides a solution that can effectively fill high aspect ratio gaps between waveguide cores of a PLC device. The present invention provides a solution that promotes better reflow characteristics during the anneal process and better gap filling capability without causing higher corrosion rates. The present invention provides solution that can fill high aspect ratio gaps without adding an excessive amount of time to the overall device fabrication process.
In one embodiment, the present invention is implemented as a dual layer top clad fabrication method for a PLC. The method includes a first step of providing a high flow rate of a Boron dopant gas for the first top cladding layer deposition process. Then, a low flow rate of a Boron dopant gas is provided for the second top cladding layer deposition process. The second top cladding layer deposition process is performed directly on the first top cladding layer deposition. The first and second top cladding layer are combined to form a dual layer top clad of the PLC having a high Boron portion covering a plurality of optical cores and a low Boron portion covering the high Boron portion.
The first top cladding layer deposition process can comprise three deposition and anneal cycles using the high flow rate of the Boron dopant gas. The three deposition and anneal cycles are used to fill gaps between the plurality of optical cores of the PLC. The second top cladding layer deposition process comprises a single deposition and anneal cycle using the low flow rate of the Boron dopant gas. The low Boron portion is configured to cover the high Boron portion and protect the high Boron portion from corrosion. The Boron dopant gas can comprise B2H6 or B(OCH3)3 tetramethyl borate (TMB).
Thus the dual layer top clad process can effectively fill high aspect ratio gaps between waveguide cores with better corrosion resistance. The high Boron concentration in the first portion of the top clad promotes better reflow characteristics during the anneal process and better gap filling capability. The better gap filling capability reduces the number of deposition and anneal cycles needed to fill the high aspect ratio gaps. The low Boron concentration in the second portion of the top clad protects the PLC from corrosion.